1. Field of the Invention
The present invention relates to integrated circuits and, more particularly, to a laser powered integrated circuit.
2. Description of the Related Art
Integrated circuits typically have power supply circuits that receive, regulate, and distribute power to the functional circuits within the integrated circuits. Functional circuits commonly extract power from the power supply via a PMOS transistor, where the gate of the PMOS transistor is used to control whether a current from the power supply can flow through the transistor.
FIG. 1 shows a schematic diagram that illustrates a prior-art functional circuit 100. As shown in FIG. 1, circuit 100 includes a PMOS transistor 110 that has a source 110A connected to a power supply voltage VCC, a gate 110B connected to an input node NIN, and a drain 110C connected to an output node NOUT. As further shown in FIG. 1, circuit 100 also includes an NMOS transistor 112 that has a source 112A connected to ground, a gate 112B connected to the input node NIN, and a drain 112C connected to the output node NOUT.
In operation, when the voltage on the gates 110B and 112B of transistors 110 and 112 rises and is within a PMOS threshold voltage of the supply voltage VCC, transistor 110 is turned off, and transistor 112 is turned on. As a result, transistor 112 pulls the voltage on the output node NOUT down to ground.
On the other hand, when the voltage on the gates 110B and 112B of transistors 110 and 112 falls and is within an NMOS threshold voltage of ground, transistor 110 turns on and transistor 112 turns off. As a result, transistor 110 sources a current to the output node NOUT that pulls up the voltage on the output node NOUT.
Although the operation of circuit 100 is simple and straightforward, the power supply circuits required to provide power to the source of PMOS transistor 110 have a number of significant associated issues. Some of the issues include a dynamic IR drop that is related to variations in the power supply, ground bounce, and latch up that is related to power supply bouncing.
In addition, a wider library characterization should be used to take into account the wider guard banding of gate characteristics in the time domain that is due to power supply voltage variation. Further issues include power supply related noise, cross talk, and joule heating. Dynamic or static power supply variation can also lead to clock skew and related timing closure difficulties.
Additional issues include an elevated area density due to the area requirement of the power supply routing metal, vias, and contacts, and the increased complexity, including IC CAD complexity, due to the power supply routing. There are also wider electro-migration requirements due to the power supply requirements, and non-isothermal heating related glitches that have no available debug mechanism.
As a result, there is a need for an approach of providing power to the functional circuits of an integrated circuit that reduces or eliminates the above noted issues that are associated with conventional power supply circuits.